1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a method for driving a plasma display panel, for making a stable address discharge.
2. Background of the Related Art
The plasma display panel (hereafter called as “PDP”) is a device for displaying a picture including characters, or graphics by making phosphor luminescent by a UV ray emitted when inert gas mixture (He+Xe, Ne+Xe, or He+Xe+Ne) discharges. The PDP has advantages in that fabrication of a large sized thin screen is easy, and provides a significantly improved picture quality owing to recent technical development.
Typically, the PDP is provided with three electrodes driven by an AC voltage, which is called as an AC surface discharge type PDP. The AC surface discharge type PDP has advantages of a low voltage drive and a long lifetime because wall charges are accumulated on a surface during discharge, and electrodes are protected from sputtering caused by the discharge.
A discharge cell of a related art AC PDP of surface discharge type having 3-electrodes is provided with a scan electrode Y and a sustain electrode Z formed on a front substrate (not shown), and an address electrode X formed on a back substrate (not shown). The address electrode X is formed in a direction perpendicular to a direction of the address electrode X and the scan electrode Y.
There are a front dielectric (not shown) and a protective layer (not shown) stacked on the front substrate having the scan electrode Y and the sustain electrode Z formed in parallel. The wall charges generated in the plasma discharge are accumulated on the front dielectric.
The protective layer prevents the front dielectric from damage caused by sputtering during the plasma discharge, and enhances an emissive efficiency of secondary electrons. In general, the protective film is formed of magnesium oxide MgO.
There are back dielectric (not shown) and barrier ribs (not shown) on the back substrate having the address electrode X formed thereon. Phosphor (not shown) is coated on surfaces of the back dielectric and the barrier ribs.
The barrier ribs are formed in parallel with the address electrode X, for prevention of optical, or electrical interference between adjacent cells on the back substrate. That is, the barrier ribs prevent leakage of the UV ray and visible light produced by discharge to adjacent discharge cells.
The phosphor is excited by the UV ray emitted during the plasma discharge, to emit one of red, green, and blue visible lights. A discharge space formed between the two substrates has inert gas mixture (He+Xe, Ne+Xe, or He+Xe+Ne) injected therein for gas discharge.
Referring to FIG. 1, the discharge cells have an array of a matrix. As shown in an electrode arrangement in FIG. 1, one discharge cell 1 is provided with scan electrodes Y1-Ym and sustain electrodes Z1-Zm running in parallel, and a discharge cell at every crossing part of the parallel two electrodes Y1-Ym and Z1-Zm, and the address electrodes X1-Xm.
The scan electrode lines Y1˜Ym are driven progressively, and the sustain electrode lines Z1˜Zm are driven in common. The address electrode lines X1˜Xn are driven, with odd numbered lines and even numbered lines divided.
The AC PDP of surface discharge type having 3-electrodes has a driving time period divided into a plurality of sub-fields for displaying one frame of a particular gradation. The gradation can be displayed by making emission of light for a number of times proportional to a weight of a video data in each of sub-field duration.
FIG. 2 illustrates one example of a frame structure for driving a related art PDP.
Referring to FIG. 2, the AC PDP of surface discharge type having 3-electrodes is driven, with one frame time period divided into 12 sub-fields (SF1˜SF12). More particularly, the one frame time period of each discharge cell 1 is divided into sub-fields of selective write type (SF1˜SF6), and sub-fields of selective erase type (SF7˜SF12).
The sub-fields of selective write type display low gradations by sustaining discharges at selected and turned on discharge cells, and the sub-fields of selective erase type display high gradations by turning off cells turned on in a last selective write sub-field out of the sub-fields of selective write type.
The first sub-field SF1 is divided into a reset period for resetting an entire screen, a selective write address period for lighting selected discharge cells, a sustain period for sustaining sustain discharges at discharge cells selected by the address discharge, and an erase period for erasing the sustain discharge.
Each of the second to fifth sub-fields SF2˜SF5 is divided into a selective write address period, a sustain period, and an erase period. The sixth sub-fields SF6 is divided into a selective write address period, and a sustain period.
Particularly, in the first to sixth sub-fields SF1˜SF6, the selective write address period and the erase period in each of the sub-fields SF1˜SF6 are set in the same ratios. However, the sustain period of each of the sub-fields SF1˜SF6 is given a time weight different from each other in a ratio of 2 to the Nth power (N=0, 1, 2, 3, - - - , 7). That is, the sustain periods are increased in ratios of 1:2:4:8:16:32:64:128 from the first sub-field SF1 to the eighth sub-field SF8.
Each of the next seventh to twelfth sub-fields SF7˜SF12 is divided into a selective erase address period for turning off selected discharge cells without a writing period, and a sustain period for sustaining discharges at the discharge cells except the discharge cells selected by the address discharge.
In the seventh to twelfth sub-fields SF7˜SF12, the selective erase address period and the sustain period are set to be in the same ratios. Particularly, the sustain period of each of the seventh to twelfth sub-fields SF7˜SF12 is set to have the same luminance relative ratio with the sixth sub-field SF6.
The seventh to twelfth sub-fields SF7˜SF12 driven in the selective erase type are required that a prior sub-field is in a turned on state without fail every time the sub-fields are continuous for turning off unnecessary discharge cells. For an example, for lighting the seventh sub-field SF7, it is required that the sixth sub-field SF6 driven in selective write type is turned on. After having the sixth sub-field SF6 turned on, unnecessary discharge cells out of the seventh to twelfth sub-fields SF7˜SF12 are turned off in a progression.
For using the selective erase sub-fields ESF SF7˜SF12 of selective erase type, it is required that the discharge cells turned on in the sixth sub-field SF6, the last selective write field WSF is sustained in a turned on state by sustain discharges.
Accordingly, the seventh sub-field requires no separate writing discharge for the selective erase addressing. Moreover, the eighth to twelfth sub-fields SF8˜SF12 also turn off cells turned on in a prior sub-field without writing on entire screen.
FIG. 3 illustrates a waveform diagram showing on example of driving waveforms in driving a PDP according to the frame in FIG. 2.
Referring to FIG. 3, in the reset period of the selective write sub-field SW, a reset pulse of ramp-up waveform RP is provided to the scan electrode lines Y in an initial set-up period SU. The reset pulse of ramp-up waveform RP causes a set-up discharge in discharge cells on entire screen, to accumulate wall charges of positive polarity (+) on the address electrode lines X and the sustain electrode lines Z, and wall charges of negative polarity (−) on the scan electrode lines Y.
Then, in the set-down period SD, a reset pulse of ramp-down waveform (−RP) is provided to the scan electrode lines Y. The reset pulse of ramp-down waveform (−RP) has a declining waveform starting from a voltage of positive polarity lower than a peak voltage of a reset pulse of ramp-up waveform (RP) after the reset pulses of ramp-up waveform (RP) is provided. The reset pulse of ramp-down waveform (−RP) drops down to a first scan reference voltage Vyw1 of negative polarity (−).
While the reset pulse of ramp-down waveform (−RP) is provided to the scan electrode lines Y, a first DC voltage of positive polarity (+) is provided to the sustain electrode lines Z. That is, at the time the reset pulse of ramp-down waveform (−RP) is provided, the first DC voltage of positive polarity (+) is started to be provided to the sustain electrode lines Z. The first DC voltage Zdc1 is sustained until the reset pulse of ramp-down waveform (−RP) reaches to the first scan reference voltage Vyw1 of negative polarity.
The reset pulse of ramp-down waveform (−RP) causes a weak erasure discharge (=set-down discharge) at the discharge cells to erase a portion of the wall charges from respective electrodes X, Y, and Z formed excessively, so that the wall charges remain at each of the discharge cells uniformly enough to cause stable address discharge by the set-down discharge.
In the address period of selective write sub-field SW, a second DC voltage Zdc2 of positive polarity (+) is provided to the sustain electrode lines Z. The second DC voltage Zdc2 has a level lower than the first DC voltage Zdc1.
During the second DC voltage Zdc2 is provided to the sustain electrode lines Z, a selective write scan pulse SWSP of negative polarity (−) is provided to the scan electrode lines Y, and a selective write data pulse DP of positive polarity (+) synchronous to the selective write scan pulse SWSP of negative polarity (−) is provided to the address electrode lines X. In this instance, the selective write scan pulse SWSP of negative polarity (−) has a level of a second scan reference voltage Vyw2 lower than the first scan reference voltage Vyw1 provided in the set-down SD period.
As a voltage difference of the selective write scan pulse SWSP and the selective write data pulse SWDP is added to a voltage caused by the wall charges produced in the reset period, there is an address discharge caused at the discharge cell the selective write data pulse SWDP is provided thereto.
Wall charges are formed at the discharge cells selected by the address discharge enough to cause discharge when the sustain voltage Vs is provided thereto. For causing the sustain discharge at the discharge cells selected by the address discharge, a sustain pulse SUSPy, or SUSPz is provided to the scan electrode lines Y and the sustain electrode lines Z alternately in the sustain period of selective write sub-field SW.
The discharge cells selected by the address discharge has a sustain discharge, i.e., a display discharge, occurred between the scan electrode line Y and the sustain electrode line Z every time the sustain pulse SUSPy, or SUSPz is provided thereto as a voltage owing to the sustain pulse SUSPy, or SUSPz is added to wall voltages at the discharge cells.
The sustain pulse SUSPy, or SUSPz has a pulse width in a range of 2-3 μs for stabilization of the sustain discharge. This is because, though discharges are occurred substantially within a range of 0.5-1 μs after the time the sustain pulse SUSPy, or SUSPz is applied, it is required that the sustain pulse SUSPy, or SUSPz maintains the sustain voltage Vs for a period substantially in a range of 2-3 μs after the discharges for forming the wall charges enough to cause the next discharge.
Then, the reset periods of the selective erase sub-fields SE1, SE2, - - - , are omitted, and the address period is started, immediately.
In the address period of the selective erase sub-fields SE1, SE2, - - - , selective erasure pulses SESP and SEDP are provided to the scan electrode lines Y and the address electrode lines X respectively, for turning off the discharge cells. In more detail, the selective erase scan pulse SESP of negative polarity (−) is provided to the scan electrode lines Y, and the selective erase data pulse SEDP of positive polarity (+) synchronous to the selective erase scan pulse SESP is provided to the address electrode lines X. In this instance, the selective erase scan pulse SESP is provided, with a level of the selective erase scan pulse SESP dropped to a level of the selective erase scan voltage −Vye higher than the scan reference voltage −Vyw.
In the sustain period of the selective erase sub-fields SE1, SE2, - - - , for causing sustain discharge at discharge cells having not turned off by the address discharge, the sustain pulse SUSPy, or SUSPz is provided to the scan electrode lines Y and the sustain electrode lines Z, alternately. However, if the next sub-field is the selective erase field SE, at an end time of the present selective erase sub-field SE, the sustain pulse SUSPy having comparatively large pulse width is provided to the scan electrode lines Y.
In the last selective erase sub-field, an erase pulse EP and a ramp pulse are provided to the scan electrode lines Y and the sustain electrode lines Z. According to this, sustain discharges at turned on discharge cells are erased. In this instance, the next sub-field of the last selective erase sub-field is the selective write sub-field SW.
FIGS. 4A˜4C illustrate forms of wall charge production in regular operation of the selective erase sub-field SE in FIG. 3.
Referring to FIGS. 4A˜4C, when the sustain discharge of one of the selective write sub-fields SW1˜SW6 is finished, wall charges are formed at all electrodes of the PDP as shown in FIG. 4A. Thereafter, at a time point t2 the scan pulse SESP and the data pulse SEDP are applied in the selective erase sub-field SE, no discharge is occurred as shown in FIG. 4B. At such a discharge cell, a sustain discharge is occurred as shown in FIG. 4C as the sustain pulse SUSPz is applied thereto at a t3 time point.
However, if the sustain voltage Vs of the sustain pulses SUSPy and SUSPz is too high, or the selective erase scan voltage −Vye is too low, an erratic discharge is occurred at the time point t2, when it is required that no discharge is occurred. That is, the erratic discharge is occurred between the scan electrode lines Y and the address electrode lines X, or between the scan electrode lines Y and the sustain electrode lines Z as shown in FIG. SA.
Such an erratic discharge acts as an erase discharge, impeding occurrence of the sustain discharge in the sustain period, resulting in a correct display of gradation on the entire PDP.